Power integrity is a very broad and confusing subject because there are so many different problems and solutions encompassed in this field. From the chip’s perspective, it’s all about the noise on the die. In this presentation, we will look at controlling the noise on the die from self-aggression noise due to core logic switching. We will look at engineering the PDN impedance profile to control this noise by interconnect design and capacitor selection and placement and how we can test our success.