HSDD-20-28 2017 week 5 HOL

• These are two hands on labs using Hyperlynx
• First one is evaluating the driver: output resistance, rise time, pacakge model
• Second one is about point to point topology and terminations
• Look at rising edge, clocks, PRBS signals and single bit response
• What is an advantage of the Vtt termination? what value of R and Vtt is optimum?