Eric Bogatin's Blog: What I Learned This Month

Last July, Bogatin Enterprises was acquired by LeCroy Corp and today, I had the honor and thrill of meeting Walter LeCroy, the founder of what has now become the supplier for the world’s highest bandwidth, real time scopes.

In 1964, Walter started up LeCroy Research Systems (LRS) to provide innovative instrumentation. Fifty years later, we are a global company with some of the industry’s top experts, pushing the envelope of practical measurement solutions.

If you have a chance during DesignCon 2012, you should stop by the LeCroy booth, #101 and say hi to the founder of one of the top scope suppliers in the world.

Walter will be around on Tues Jan 31 and Wed Feb 1. See you there!

“That’s a pretty cool benefit,” Phil Warwick, CTO of R&D Circuits, a leading edge circuit board manufacturer said at the 5-TA3 session at DesignCon 2012. He was referring to the use of 0.4 mm pitch BGA packages.

One advantage he’s identified is that differential vias with the typical drill hole size, on a 0.4 mm pitch, with surrounded return vias, results in a differential via impedance of about 85 to 120 Ohms. As long as the via stub is backdrilled, the thru part of the via will look pretty transparent, an advantage, Warwick says for 25 Gbps links.

But, the problem these higher density pitched create is narrow web for delivering the high currents required by large pin count ASICS and FPGAs. Some of the devices he builds boards for require 100 to 300 A at 0.85 v. In the narrow web between clearance holes in the power and ground planes, shoving 300 A causes hot spots which can burn out the board. “We will fry that web quickly,” Warwick said and backed up his comment with graphic images of splattered copper that used to be a narrow web.

To manage a low DC IR drop from the planes to the center of the package, Warwick has worked with chip and package designers to implement a new ball topology he calls “slats”. Rather than scatter the power and ground balls in a checkerboard arrangement, typically recommended to reduce the inductance in the PDN feed to the package, he suggests using grouped rows of power balls and ground balls, as shown in the figure above. This enables wide channels in the power and ground planes and low IR drop.

Temperature rise measurements on boards produced with this slat topology showed only a 20 degree rise with 200A of DC current.

Warwick suggests that while it is important to pay careful attention to specific board features to enhance 28 Gbps data paths, there are still important design tradeoffs to manage all the way down to DC. Understanding all the design-performance cost tradeoffs become increasingly important as the data rates, the pin counts and the power requirements all increase in leading edge designs.

DesignCon 2012 Tues Morning:9-TAI. Hai Lan from Rambus gave a great presentation on how the power supply noise influences the jitter for a 6.4 Gbps single-ended GDDR memory interface. He calls this noise Power Supply Induced Jitter (PSIJ)

Of course, the details of how power supply noise affects the jitter depends on many factors- each element that contributes to the system- the PLL, the clock, the pushout and pull in of the TX and the coupling between the power supplies.

Hai looked at a number of the pieces of the system and evaluated the noise spectrum on the PDN, the jitter sensitivity of each component and the resulting jitter to be expected.

Not surprising, the worst PDN noise is going to be when the clock bursts happen at a 50% duty cycle, with a repeat frequency matching a peak in the impedance profile. This gives the largest PDN noise, which Hai estimated could be as large as 65 mV in his specific example.

Next is the jitter sensitivity of the elements. Though it depends so much on the chip technology and features, as a rough estimate for his examples, he sees about 0.3 to 0.5 psec/mV of jitter sensitivity, on the PLL, the clock and on the supply to the TX.

When looking at the complete system including all the noise sources, Hai says that in some cases, for these GDR circuits, PSIJ noise could contribute to as much as 24% of the UI as jitter. If you don’t include the PDN noise analysis in the jitter budget, you may be rudely surprised when you build and test your product.

My first hallway conversation at DesignCon 2012 on Monday Jan 30 was with Barry Williams, an experienced hardware engineer with Oracle. Our chat quickly went to the problem we see with many young engineers who don’t have a strong foundation in the principles of signal integrity.

They do a simulation, and have no idea what is good or what is bad, and so they accept everything out of their simulator.

As veterans of many fires, we both recognize the equal value of each leg of the three legged stool of understanding, measurement and simulation. Successful engineers, efficient at solving problems, are well verse equally in these three areas. If you can look at all problems from the perceptive of these three terms, you will have confidence in your results.

In my column, Bogatin’s Ten Rules, My rule #9 is never do a measurement or simulation without first anticipating what you expect to see. If you are wrong, it tells you either there is something wrong with your set up or the measurement, or with your understanding. Either way, in exploring the difference, you will learn something new. If you are right, you get a nice warm feeling that you really understand what is going on.

If you want to expand your understanding of SI principles, check out the classes we just posted at www.beTheSignal.com.

I’ve assembled a few of the signal integrity experts I turn to when I have a technical question to join me in an “Ask the Experts” panel at DesignCon 2012.

On Wed Feb 1 at 2:00-2:45 pm in the ChipHead Theater, I will moderate a panel discussion, “Ask the experts, anything goes”. Included on the panel of experts are:

• Scott McMorrow, Teraspeed
• Bruce Archambeault, IBM
• Jim Nadolny, Samtec
• Yuriy Shlepnev, Simberian
• Ravi Kollipara, Rambus
• Jianmin Zhang, Cisco
• Jason Miller, Oracle

I have the best job in the world. I get to solicit questions from the audience and pose them to the panel. As an experiment, I will also accept questions by twitter.

On twitter, send your questions to @beTheSignal and use #SIDoctorIsIn.

If you heard a design guideline that just didn’t sound right, if you just released a design to fab and are staying up at night worrying about an iffy design feature, if you need the correct answer to settle an argument with your design team, come to this once in a lifetime opportunity to ask the world’s top signal integrity experts, personally.

You are guaranteed to learn something new and important from this exciting panel discussion.

• Should decoupling capacitors go on top of the board, or on the bottom of the board?
• Should DC blocking caps go near the TX or the RX?
• Should meander lines have a few long loops or many short loops?
• Which is better, tight or loose coupled differential pairs?
• Does a microstrip transmission line really cause EMC failures?
• What are the three most commons sources of failure in DDR3 designs?
• Where does the return current in a common signal go when it transitions from a circuit board to an unshielded twisted pair cable

Of course, the answer is always, “…it depends”, but learn from the experts, on what it depends.

See you there!

One of the many hats I wear is as an Adjunct Professor at Printed Circuit University.  This is the brainchild of Pete Waddell, Dean of PCU, publisher of Printed Circuit Design and Fabrication Magazine and president of UP Media Group. His goal is to create a one-stop-shop for training on all aspects of printed circuit board technology, including fabrication, processing, materials, assembly and design.

Many of the signal integrity online lectures I created over the last ten years and online versions of my popular curricula, both introductory and advanced, were contributed to PCU and are currently available to registered students at PCU.

As an experiment in online education, Pete and his team, lead by Mike Buetow, editor of Printed Circuit Design and Fabrication Magazine, invited me to hold office hours at PCU. I see this as a chance to sort of meet up with any past, present or future students over a cup of coffee and chat about signal integrity.

When I teach classes I always enjoy listening to and answering questions from students. I learn what is important that I may not have included in my lecture and what is confusing. I use the questions I hear as feedback to constantly evolve and improve my classes. And, I confess, it still gives me a distinct pleasure to see a student achieve that “ah ha!” moment of insight when a complex principle suddenly crystalizes into clarity.

So, come join me for a cup of coffee and a chat about signal integrity, at my first ever office hours. Any questions are fair game. I’m looking forward sharing some of my hard earned insights into the practical effects of high speed signals interacting with interconnects and learning a few new things from you.

You must be a member of the PCU community to participate, but membership is free. Be sure to visit the PCU site before Jan 26 at 2 pm EST to set up your free account if you want to join us on time! If you miss the live office hours, the chat will be recorded and available as an archive. Check it out!

As an added bonus, if you can’t make it, tweet me your question before my office hours, I’ll answer them during the live event and it will be posted in the archive for you to read.

Tweet me @beTheSignal.com and use #SIDoctorIsIn.

You can’t miss this one of a kind event at DesignCon 2012, scheduled for Tues, Jan 30, 2012 at 1:00 to 1:45 in the Chip Head Theater.

In 45 minutes, I will walk you through How Return Loss Gets its Ripples.

If you have every looked at a plot of the return loss of almost any interconnect you’ve seen the distinctive features of ripples. The return loss goes through peaks and dips. Sometimes you see these ripples in the insertion loss, sometimes not. It doesn’t matter if you look at measured or simulated data. Why is this?

What is the feature of the interconnect that causes this S-parameter feature? Why does it have the spacing it has or the magnitude of the peaks? What can you read from the front screen about the interconnect from the peaks and dips?

All will be made clear in this 45 minute quick presentation.

As a special experiment, I will be taking questions by tweets. Send your questions on this topic to @beTheSignal and use hashtag #ReturnLossRipples

See you there!

The perfect cases for every luddite to carry their iPod, camera and laptop, available from Retro to Go.

I am not a Luddite. I embrace technology: from my iPhone, iPad and hi end PC to the latest, state of the art, high-end, simulation software I use every day. But I’ve only barely dipped my toe in social media, up to now.

When the pressure to write a regular blog became too great to resist, I became a blogger and for the last four years, post regular on my signal integrity blog at beTheSignal.com/blog. I’ve slowly learned the distinction of content and my voice in a blog, as compared to a column, feature article or book.

Blogs, I’ve learned, are for content you might want to “chat about” when you talk to a colleague you haven’t seen for a while. It’s a more informal, casual style, with a short, single topic focus.

I use my signal integrity blog on beTheSignal to post my comments on articles or books I’ve recently read, or a cool web site I saw. If I had an interesting technical discussion with someone, I write it up, to share it with a broader community. If I learned something new from these activities, I think others involved in high speed digital design or signal integrity, might find the information of value as well.

But that’s been the extent of my involvement in social media. We tried creating a Facebook page for beTheSignal, but we never figured out how to successfully utilize it- for our benefit or for our customers.

I am a big fan of Leo Laporte and his most popular show, This Week in Tech (TWiT). A few years ago, he’d focus on PCs, then the theme migrated to cell phones, then it was Facebook and for the last year, it’s been Twitter.

As twitter grew in popularity and influence, I got more and more worried- what was I missing?

Even with many of my younger students telling me I should have a Twitter account, I hesitated, reluctant to dive in, especially after crashing and burning on Facebook.

But now, my new LeCroy cousins, Hilary Lustig (@HilaryLustig) and Jeremy Graef,  twisted my arm and dragged me kicking and screaming into the 21st century, convincing me I need to Tweet. But with them to back me up and guide me along this new path, I decided to take the plunge.

I can now say, I am a Twitter. My handle is @beTheSignal.com.

I have great plans for my tweets- and I promise, they are only going to be good stuff, well worth the ten second interruption these tweets create.

If you care about signal integrity, high speed electronics and technology, you can follow me into the 21st century @beTheSignal.

The first thing I think of when I think of the New Year is DesignCon. Every year for the last 20, at the end of the year, I’ve been in the middle of wrapping up preparation for the upcoming DesignCon. I started my involvement with DesignCon before it was DesignCon, back in the days when it was the HP High Speed Digital Symposium.

Each year, the conference is like a giant class reunion party. I get to hang out with folks I see once a year, with whom I’ve shared adventures, last-minute deadline-driven adrenaline-pumped cramming-sessions and sweating in front of a large audience filled with folks far more expert than I, challenging what I just spent a year working on. Gee, this sounds a lot like my orals exam in graduate school…

Not a single DesignCon goes by that I don’t learn something significant that I never thought about before and at which I generate more partnerships and projects to carry me easily through the year to the next DesignCon.

At this year’s DesignCon, in addition to participating in two papers:

13-TP6:   A Practical Approach for Using Circuit Board Qualification Test Results to Accurately Simulate High Speed Serial Link Performance 

9-TP5: A Robust Method for Addressing 12 Gbps Interoperability for High-Loss and Crosstalk-Aggressed Channels

I am trying two new activities.

On Tues at 1-1:45 pm in the Theater, I will be doing a “speed training” session. In 45 minutes every attendee will learn how return loss gets its ripples. This is the most important feature of return loss and tells a lot about the interconnect. You may even see a leopard or two….

On Wed at 2:00-2:45pm in the Theater, I will moderate a panel discussion, “Ask the experts, anything goes”. I asked a few of the folks I go to with my SI questions to hang around and field questions from the audience. They can be as basic as what is inductance, to as complicated as, where does the return current in a common signal go when it transitions from a circuit board to an unshielded twisted pair cable. Anything goes….

If you want to have a fun time, join me at these events at DesignCon. For your convenience, I posted all the links to my events on my home page as well: www.beTheSignal.com. When I am not attending an event, find me at the LeCroy booth, #101.

See you there!

December 2011 was a busy travel month for me. I gave a series of classes in India and Israel to packed rooms. Here I am in the S-parameters for SI class in Herzilya, Israel.

At this point in the class, I was showing how a simple approximation can be used to estimate the insertion loss in single-ended or differential channels based on the line width and the material properties.

The insertion loss per length, in dB/inch, for a 50 Ohm single-ended or 100 Ohm differential line is roughly:

S21 per length = 1/w x sqrt(f) + 2.3 x Df x sqrt(Dk) x f    dB/inch

with w in mils and f in GHz

For example, at 1 GHz, if the line width is 8 mils in FR4, the insertion loss per length is about

S21 per length = 1/8 x sqrt(1) + 2.3 x 0.02 x sqrt(4) x f dB/inch = 0.12 + 0.09 = 0.2 dB/in

The plot on the screen at this point in the lecture is a comparison of the measured insertion loss per inch from two different lines and this simple approximation. The results are pretty close.

This approximation is not meant to be a substitute to a good field solver, but it  helps give a rough idea of what to expect in real interconnects. It’s real value is that “…sometimes an OK answer NOW! is better than a good answer late.”

For more details on our other classes, check out our web site at www.beTheSignal.com